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Data Sheet


Mixtile Core 3588E is a compact SoM powered by Rockchip 3588, a high-performance low-power AIoT processor that integrates quad-core Cortex-A76 and quad-core Cortex-A55. Capable of delivering up to 6 TOPS AI performance, Core 3588E targets a wide range of applications, including ARM-based PCs, Edge Computing devices, personal mobile internet devices, and other digital multimedia applications.

Main Features

  • Excellent video processing capabilities
    • 8Kp60 video decoding (H.264/H.265/VP9)
    • 8Kp30 video encoding (H.264/H.265)
    • JPEG encoding and decoding
  • Robust image processing capabilities
    • High Dynamic Range (HDR)
    • 3A
    • LSC
    • 3DNR, 2DNR
    • Sharpening
    • Dehaze
    • Fisheye correction
    • Gamma correction
    • Image preprocessor and postprocessor
  • Strong AI performance
    • 6 TOPS
    • INT4/INT8/INT16/FP16
    • TensorFlow/MXNet/PyTorch/Caffe
  • High-speed interfaces: PCIe 3.0 x4 lanes + PCIe 2.1 x1 lane

Technical Specifications

Technical itemsSpecifications
CPUQuad-core Cortex-A76 (2.4 GHz) + Quad-core Cortex-A55, Neon and FPU
GPUArm Mali-G610 MP4 with support for OpenGL ES3.2, OpenCL 2.2, Vulkan1.2
NPURK NN, 6 TOPS NPU with support for TensorFlow, Caffe, TFLite, PyTorch, ONNX NN, Android NN
Memory4 GB, 8 GB, 16 GB, or 32 GB 64-bit LPDDR4
Storage32 GB, 64 GB, or 128 GB eMMC 5.1 flash storage
Supported OSDebian 11, Android 11, Ubuntu 22.04, and Armbian 23.07
Supply power5 V DC
Display1x HDMI interface + 1x DP/eDP combo interface, up to 7680 x 4320@60 Hz for HDMI and DP, and 3840 x 2160@60 Hz for eDP
Camera3x 4-lane or 5x 2-lane MIPI CSI interfaces @ 2.5 Gbps/lane
Network10/100/1000 BASE-T
USB1x USB 3.0 (Gen1), 3x USB 2.0
PCIePCIe 3.0 x4 + PCIe 2.1 x1
Others– UART DEBUG x1, UART+flow control x2
– SPI x2
– I2C x4
– CAN x1
– I2S x4
– SD 4.0, SDHOST 4.0, and SDIO 3.0
– PWM x3, GPIO x15
Connector260-pin SO-DIMM edge connector, compatible with Jetson TX2 NX
Dimensions69.6 mm x 45 mm
Temperature– Operating: 0°C to 80°C
– Storage: -20°C to 85°C
Relative humidity– Operating: 10% to 90%
– Storage: 5% to 95%

Functional Description


  • Quad-core ARM Cortex-A76 MPCore processor and quad-core ARM Cortex-A55 MPCore processor, both are high-performance, low-power and cached application processors
  • DSU (DynamIQ Shared Unit) comprises the L3 memory system, control logic, and external interfaces to support a DynamIQ cluster
  • Full implementation of the ARM architecture v8-A instruction set, ARM Neon Advanced SIMD (single instruction, multiple data) support for accelerating media and signal processing
  • ARMv8 Cryptography Extensions
  • TrustZone technology support
  • Integrated 64KB L1 instruction cache, 64KB L1 data cache and 512KB L2 cache for each Cortex-A76
  • Integrated 32KB L1 instruction cache, 32KB L1 data cache and 128KB L2 cache for each Cortex-A55
  • Quad-core Cortex-A76 and Quad-core Cortex-A55 share 3MB L3 cache
  • Eight separate power domains for CPU core system to support internal power switch and externally turn on/off based on different application scenarios:PD_CPU_0: 1st Cortex-A55 + Neon + FPU + L1/L2 I/D Cache
    • PD_CPU_1: 2nd Cortex-A55 + Neon + FPU + L1/L2 I/D Cache
    • PD_CPU_2: 3rd Cortex-A55 + Neon + FPU + L1/L2 I/D Cache
    • PD_CPU_3: 4th Cortex-A55 + Neon + FPU + L1/L2 I/D Cache
    • PD_CPU_4: 1st Cortex-A76 + Neon + FPU + L1/L2 I/D Cache
    • PD_CPU_5: 2nd Cortex-A76 + Neon + FPU + L1/L2 I/D Cache
    • PD_CPU_6: 3rd Cortex-A76 + Neon + FPU + L1/L2 I/D Cache
    • PD_CPU_7: 4th Cortex-A76 + Neon + FPU + L1/L2 I/D Cache
  • Three isolated voltage domains to support DVFS, one for A76_0 and A76_1, one for A76_2 and A76_3, the other for DSU and Cortex-A55

Memory Organization

  • Internal on-chip memory
    • BootRom
      • Support system boot from the following interfaces:
        • SPI interface
        • eMMC interface
        • SD/MMC interface
      • Support system code download by the following interface:
        • USB OTG interface
    • Share Memory in the voltage domain of VD_LOGIC
    • PMU SRAM in VD_PMU for low power application
  • External off-chip memory
    • Dynamic Memory Interface
      • Compatible with JEDEC standards LPDDR4/LPDDR4X/LPDDR5
      • Support four channels, 16 bits data widths for each channel
      • Support up to 2 ranks (chip selects) for each channel
      • Totally up to 32 GB address space
      • Low power modes, such as power-down and self-refresh for SDRAM
    • eMMC Interface
      • Fully compliant with JEDEC eMMC 5.1 and eMMC 5.0 specification
      • Backward compliant with eMMC 4.51 and earlier versions specification
      • Support HS400, HS200, DDR50 and legacy operating modes
      • Support three data bus widths: 1 bit, 4 bits, and 8 bits
    • SD/MMC Interface
      • Compatible with SD3.0, MMC ver4.51
      • Data bus width is 4 bits
    • Flexible Serial Flash Interface
      • Support transferring data from/to serial flash device
      • Support 1 bit, 2 bits or 4 bits data bus width
      • Support 2 chips select

System Components

  • MCU (microcontroller unit)
    • Three Cortex-M0 MCUs inside RK3588:
      • MCU in VD_PMU integrate 16KB Cache and 16KB TCM
      • MCU in VD_NPU integrate 16KB Cache and 64KB TCM
      • MCU in PD_CENTER integrate 32KB TCM
    • Integrated Programmable Interrupt Controller, all IRQ lines connected to GIC for CPU also connect to MCU in VD_PMU(PMU_M0) and PD_CENTER(DDR_M0)
    • Integrated Debug Controller with JTAG interface
  • CRU (clock & reset unit)
    • Support total 18 PLLs to generate all clocks
    • One oscillator with 24 MHz clock input
    • Support clock gating control for individual components
    • Support global soft-reset control for whole chip, also individual soft-reset for each component
  • PMU (power management unit)
    • Multiple configurable work modes to save power by different frequency or automatic clock gating control or power domain on/off control
    • Lots of wakeup sources in different modes
    • Support 10 separate voltage domains
    • Support 45 separate power domains, which can be powered up/down by software based on different application scenes
  • Timer
    • Support 12 secure timers with 64 bits counter and interrupt-based operation
    • Support 18 non-secure timers with 64 bits counter and interrupt-based operation
    • Support two operation modes: free-running and user-defined count for each timer
    • Support timer work state checkable
  • PWM
    • Support 16 on-chip PWMs (PWM0~PWM15) with interrupt-based operation
    • Programmable pre-scaled operation to bus clock and then further scaled
    • Embedded 32-bit timer/counter facility
    • Support capture mode
    • Support continuous mode or one-shot mode
    • Provide reference mode and output various duty-cycle waveforms
    • Optimized for IR application for PWM3, PWM7, PWM11, PWM15
  • Watchdog
    • 32-bit watchdog counter
    • Counter counts down from a preset value to 0 to indicate the occurrence of a timeout
    • Watchdog timer (WDT) can perform two types of operations when timeout occurs:
      • Generate a system reset
      • First generate an interrupt. If this is not cleared by the service routine by the time a second timeout occurs, then generate a system reset
    • Totally five watchdogs for CPU and MCU
  • Interrupt controller
    • Support 12 PPI interrupt sources and 480 SPI interrupt sources input from different components inside RK3588
    • Support 16 software-triggered interrupts
    • Input interrupt level is fixed, high-level sensitive for SPI and low-level sensitive for PPI
    • Support different interrupt priorities for each interrupt source, and they are always software-programmable
  • DMAC
    • Micro-code programming based DMA
    • Linked list DMA function is supported to complete scatter-gather transfer
    • Support data transfer types including memory-to-memory, memory-to-peripherals, peripherals-to-memory
    • Totally three embedded DMA controllers for peripheral system
    • Features of each DMAC:
      • Support 8 channels
      • 32 hardware request from peripherals
      • 2 interrupt output
      • Support TrustZone technology and programmable secure state for each DMA channel
  • Secure System
    • Embedded two cipher engines
      • Support Link List Item (LLI) DMA transfer
      • Support SHA-1, SHA-256/224, SHA-512/384, MD5, SM3 with hardware padding
      • Support HMAC of SHA-1, SHA-256, SHA-512, MD5, SM3 with hardware padding
      • Support AES-128, AES-192, AES-256 encrypt & decrypt cipher
      • Support DES & TDES cipher, with ECB/CBC/OFB/CFB mode
      • Support up to 4096 bits PKA mathematical operations for RSA/ECC/SM2
      • Support generating random numbers
    • Support keyladder to guarantee key secure
    • Support data scrambling for all DDR types
    • Support secure OTP
    • Support secure debug
    • Support secure DFT test
    • Support secure OS
    • Except CPU, the other masters in the SoC can also support security and non- security mode by software-programmable
    • Some slave components in SoC can only be addressed by security master and the other slave components can be addressed by security master or non-security master by software-programmable
    • System SRAM (share memory), part of space is addressed only in security mode
    • External DDR space can be divided into 16 parts, each part can be software-programmable to be enabled by each master
  • Mailbox
    • Three mailboxes in SoC to service CPU and MCU communication
    • Support four mailbox elements per mailbox, each element includes one data word, one command word register and one flag bit that can represent one interrupt
    • Provide 32 lock registers for software to use to indicate whether mailbox is occupied
  • Decompression
    • Support for decompressing GZIP files
    • Support for decompressing LZ4 files, including the General Structure of LZ4 Frame format and the Legacy Frame format
    • Support for decompressing data in DEFLATE format
    • Support for decompressing data in ZLIB format
    • Support Hash32 check in LZ4 decompression process
    • Support the limit size function of the decompressed data to prevent the memory from being maliciously destroyed during the decompression process

Video Codec

  • Video Decoder
  • Real-time video decoder of MPEG-1, MPEG-2, MPEG-4, H.263, H.264, H.265, VC-1, VP9, VP8, MVC, AV1
  • MMU Embedded
  • Multi-channel decoder in parallel for less resolution
  • H.264 AVC/MVC Main10 L6.0 : 8K@30fps (7680 x 4320)2
  • VP9 Profile0/2 L6.1 : 8K@60fps (7680 x 4320)
  • H.265 HEVC/MVC Main10 L6.1 : 8K@60fps (7680 x 4320)
  • AVS2 Profile0/2 L10.2.6 : 8K@60fps (7680 x 4320)
  • AV1 Main Profile 8/10bit L5.3. : 4K@60fps (3840 x 2160)
  • MPEG-2 up to MP : 1080p@60fps (1920 x 1088)
  • MPEG-1 up to MP : 1080p@60fps (1920 x 1088)
  • VC-1 up to AP level 3 : 1080p@60fps (1920 x 1088)
  • VP8 version2 : 1080p@60fps (1920 x 1088)
  • Video Encoder
    • Real-time H.265/H.264 video encoding
    • Support up to 8K@30fps
    • Multi-channel encoder in parallel for less resolution

JPEG Codec

  • JPEG Encoder
    • Baseline (DCT sequential)
    • Encoder size is from 96 x 96 to 8192 x 8192 (67 Mpixels)
    • Up to 90 million pixels per second
    • Embedded four encoder units
  • JPEG Decoder
    • Decoder size is from 48 x 48 to 65536 x 65536
    • Support YUV400/YUV411/YUV420/YUV422/YUV440/YUV444
    • Support up to 1080P@280fps, and 560 million pixels per second
    • Support MJPEG
    • Embedded four encoder units

Neural Process Unit

  • Neural network acceleration engine with processing performance up to 6 TOPS
  • Include triple NPU core, and support triple core co-work, dual core co-work, and work independently
  • Support integer 4, integer 8, integer 16, float 16, Bfloat 16 and tf32 operation
  • Embedded 384KBx3 internal buffer
  • Multi-task, multi-scenario in parallel
  • Support deep learning frameworks: TensorFlow, Caffe, TFlite, PyTorch, ONNX NN, Android NN, etc.
  • One isolated voltage domain to support DVFS

Graphics Engine

  • 3D Graphics Engine
    • ARM Mali-G610 MP4
    • High performance OpenGLES 1.1, 2.0 and 3.2, OpenCL 2.2, Vulkan1.2 etc.
    • Embedded 4 shader cores with shared hierarchical tiler
    • Provide MMU and L2 Cache with 4x 256 KB size
    • The latest Valhall architecture
    • ARM Frame Buffer Compression (AFBC) 1.3
    • Support Serial Wire debug for embedded MCU
    • One isolated voltage domain to support DVFS
  • 2D Graphics Engine
    • Source format: ARGB/RGB888/RGB565/YUV420/YUV422/BPP
    • Destination formats: ARGB/RGB888/RGB565/YUV420/YUV422
    • Max resolution: 8192 x 8192 source, 4096 x 4096 destination
    • Block transfer and transparency mode
    • Color fill with gradient fill, and pattern fill
    • Alpha blending modes including global alpha, per pixel alpha (color/alpha channel separately) and fading
    • Arbitrary non-integer scaling ratio, from 1/8 to 8
    • 0, 90, 180, 270 degree rotation, x-mirror, y-mirror & rotation operation
    • ROP2, ROP3, ROP4
    • Support 4k/64k page size MMU
  • Image enhancement processor
    • Image format
      • Input data: YUV420/YUV422, semi-planar/planar, UV swap
      • Output data: YUV420/YUV422, semi-planar, UV swap, Tile mode
      • YUV down sampling conversion from 422 to 420
      • Max resolution for dynamic image up to 1920 x 1080
    • De-interlace

Video Input Interface

  • MIPI interface
    • Two MIPI DC (DPHY/CPHY) combo PHY
      • Support to use DPHY or CPHY
      • Each MIPI DPHY V2.0, 4 lanes, 4.5 Gbps per lane
      • Each MIPI CPHY V1.1, 3 lanes, 2.5 Gbps per lane
    • Four MIPI CSI DPHY
      • Each MIPI DPHY V1.2, 2 lanes, 2.5 Gbps per lane
      • Support to combine 2 DPHY together to one 4-lane
    • Support camera input combination
      • 2 MIPI DCPHY + 4 MIPI CSI DPHY (2 lanes), totally support 6 cameras input
      • 2 MIPI DCPHY + 1 MIPI CSI DPHY (4 lanes) + 2 MIPI CSI DPHY (2 lanes), totally support 5 cameras input
      • 2 MIPI DCPHY + 2 MIPI CSI DPHY (4 lanes), totally support 4 cameras input

Table 1: CSI Pin Descriptions

Pin #Pin NameSignal DescriptionDirectionPin Type
10CSI0_CLK_NCamera, CSI 0 Clock–InputMIPI D-PHY
12CSI0_CLK_PCamera, CSI 0 Clock+InputMIPI D-PHY
4CSI0_D0_NCamera, CSI 0 Data 0–InputMIPI D-PHY
6CSI0_D0_PCamera, CSI 0 Data 0+InputMIPI D-PHY
16CSI0_D1_NCamera, CSI 0 Data 1–InputMIPI D-PHY
18CSI0_D1_PCamera, CSI 0 Data 1+InputMIPI D-PHY
9CSI1_CLK_NCamera, CSI 1 Clock–InputMIPI D-PHY
11CSI1_CLK_PCamera, CSI 1 Clock+InputMIPI D-PHY
3CSI1_D0_NCamera, CSI 1 Data 0–InputMIPI D-PHY
5CSI1_D0_PCamera, CSI 1 Data 0+InputMIPI D-PHY
15CSI1_D1_NCamera, CSI 1 Data 1–InputMIPI D-PHY
17CSI1_D1_PCamera, CSI 1 Data 1+InputMIPI D-PHY
28CSI2_CLK_NCamera, CSI 2 Clock–InputMIPI D-PHY
30CSI2_CLK_PCamera, CSI 2 Clock+InputMIPI D-PHY
22CSI2_D0_NCamera, CSI 2 Data 0–InputMIPI D-PHY
24CSI2_D0_PCamera, CSI 2 Data 0+InputMIPI D-PHY
34CSI2_D1_NCamera, CSI 2 Data 1–InputMIPI D-PHY
36CSI2_D1_PCamera, CSI 2 Data 1+InputMIPI D-PHY
27CSI3_CLK_NCamera, CSI 3 Clock–InputMIPI D-PHY
29CSI3_CLK_PCamera, CSI 3 Clock+InputMIPI D-PHY
21CSI3_D0_NCamera, CSI 3 Data 0–InputMIPI D-PHY
23CSI3_D0_PCamera, CSI 3 Data 0+InputMIPI D-PHY
33CSI3_D1_NCamera, CSI 3 Data 1–InputMIPI D-PHY
35CSI3_D1_PCamera, CSI 3 Data 1+InputMIPI D-PHY
52CSI4_CLK_NCamera, CSI 4 Clock–InputMIPI D-PHY
54CSI4_CLK_PCamera, CSI 4 Clock+InputMIPI D-PHY
46CSI4_D0_NCamera, CSI 4 Data 0–InputMIPI D-PHY
48CSI4_D0_PCamera, CSI 4 Data 0+InputMIPI D-PHY
58CSI4_D1_NCamera, CSI 4 Data 1–InputMIPI D-PHY
60CSI4_D1_PCamera, CSI 4 Data 1+InputMIPI D-PHY
40CSI4_D2_NCamera, CSI 4 Data 2–InputMIPI D-PHY
42CSI4_D2_PCamera, CSI 4 Data 2+InputMIPI D-PHY
64CSI4_D3_NCamera, CSI 4 Data 3–InputMIPI D-PHY
66CSI4_D3_PCamera, CSI 4 Data 3+InputMIPI D-PHY

Table 2: Camera Control Pin Descriptions

Pin #Pin NameSignal DescriptionDirectionPin Type
213CAM_I2C_SCLCamera I2C Clock. 2.2kΩ pull-up to 3.3 V on the module.BidirOpen Drain – 3.3V
215CAM_I2C_SDACamera I2C Data. 2.2 kΩ pull-up to 3.3V on the module.BidirOpen Drain – 3.3V
116CAM0_MCLKCamera 0 Reference ClockOutputCMOS – 1.8V
114CAM0_PWDNCamera 0 Powerdown or GPIOOutputCMOS – 1.8V
122CAM1_MCLKCamera 1 Reference ClockOutputCMOS – 1.8V
120CAM1_PWDNCamera 1 Powerdown or GPIOOutputCMOS – 1.8V
  • DVP interface
    • One 8/10/12/16-bit standard DVP interface, up to 150 MHz input data
    • Support BT.601/BT.656 and BT.1120 VI interface
    • Support the polarity of pixel_clk, hsync, vsync configurable
  • HDMI RX interface
    • Single-port HDMI 2.0 RX PHY, 4 lanes, no sideband channels
    • Data rate support in HDMI 2.0 mode
      • 6 Gbps down to 3.4 Gbps
    • Data rate support in HDMI 1.4 mode
      • 3.4 Gbps down to 250 Mbps
    • HDMI 2.0 video formats
      • TMDS Scrambler to enable support for 2160p@60 Hz with RGB/YCbCr4:4:4 or YCbCr4:2:2
      • Supports YCbCr 4:2:0 to enable 2160p@60 Hz at lower HDMI link speeds
    • HDMI 1.4b video formats
      • All CEA-861-E video formats up to 1080p@120 Hz
      • HDMI 1.4b 4K x 2K video formats (3840 x 2160p@24 Hz/25 Hz/30 Hz and 4096 x 2160p@24 Hz)
      • HDMI 1.4b 3D video modes with up to 340 MHz (TMDS clock)
    • Support HDCP2.3 and HDCP1.4

Image Signal Processor

  • Video Capture (VICAP)
    • Support BT601, BT656, BT1120
    • Support receiving six interfaces of MIPI CSI/DSI, up to four IDs for each interface
    • Support five CSI data formats: RAW8/10/12/14, YUV422
    • Support three modes of HDR: virtual channel mode, identification code mode, line counter mode
    • Support RAW data through to ISP0/1
  • Maximum input
    • 48M: 8064 x 6048@15 dual ISP
    • 32M: 6528 x 4898@30 dual ISP
    • 16M: 4672 x 3504@30 single ISP
  • 3A: include AE/Histogram, AF, AWB statistics output
  • FPN: Fixed Pattern Noise removal
  • BLC: Black Level Correction
  • DPCC: Static/Dynamic defect pixel cluster correction
  • PDAF: Phase Detection Auto Focus
  • LSC: Lens shading correction
  • Bayer-2DNR: Spatial Bayer-raw De-noising
  • Bayer-3DNR: Temporal Bayer-raw De-noising
  • CAC: Chromatic Aberration Correction
  • HDR: 3-Frame Merge into High-Dynamic Range
  • DRC: HDR Dynamic Range Compression, Tone mapping
  • GIC: Green Imbalance Correction
  • Debayer: Advanced Adaptive Demosaic with Chromatic Aberration Correction
  • CCM/CSM: Color correction matrix; RGB2YUV etc
  • Gamma: Gamma out correction
  • Dehaze/Enhance: Automatic Dehaze and Effect enhancement
  • 3DLUT: 3D-Lut Color Palette for Customer
  • LDCH: Lens-distortion only in the horizontal direction
  • YUV-2DNR: Spatial YUV De-noising
  • Sharp: Image Sharpening and boundary filtering
  • CMSK: privacy mask
  • GAIN: image local gain
  • Support multi-sensor reuse ISP
  • FishEye Correction (FEC)
    • Input mode and data format
      • Support RASTER: YUV422SP, YUV422I, YUV420SP
    • Output mode and data format
      • RASTER: YUV422SP, YUV422I, YUV420SP
      • FBCE: YUV422SP, YUV420SP
    • Support 16 x 8, 32 x 16 two densities
    • Support up to 4 times reduction factor
    • Resolution 128 x 128~4095 x 4095
    • Y Interpolation: Bicubic; C Interpolation: Biliner

Display Interface

  • HDMI TX interface
    • Support one HDMI TX
    • Support 1/2/4 lanes for each interface
    • Support all the data rates: 3, 6, 8, 10 and 12 Gbps
    • Support up to 7680 x 4320@60 Hz
    • Support RGB/YUV (up to 10 bits) format
    • Support DSC 1.2a
    • Support HDCP2.3
  • DP/eDP TX interface
    • Support one DP/eDP combo interface
    • Support 1/2/4 lanes for each interface
    • Support 1.62 Gbps, 2.7 Gbps, 5.4 Gbps, and 8.1 Gbps for DP
    • Support 1.62 Gbps, 2.7 Gbps, 5.4 Gbps for eDP
    • Support up to 7680 x 4320@60 Hz for DP, 8192 x 4320@30 Hz for eDP
    • Support RGB/YUV (up to 10 bits) format for DP
    • Support RGB, YCbCr 4:4:4, YCbCr 4:2:2 and 8/10 bit per component video format for eDP
    • Support Single Stream Transport (SST) for DP
    • Support HDCP 2.3/HDCP 1.3 for DP, HDCP1.3 for eDP
  • MIPI DSI interface
    • Support 2 MIPI DPHY 2.0 interfaces
    • Support 4 data lanes and 4.5 Gbps maximum data rate per lane
    • Support max resolution 4K@60 Hz
    • Support dual MIPI display: left-right mode
    • Support RGB (up to 10 bits) format
    • Support DSC 1.1/1.2a
  • BT.1120 video output interface
    • Support up to 1920 x 1080@60 Hz
    • Support RGB (up to 8 bits) format
    • Up to 150 MHz data rate

Table 3: DSI Pin Descriptions

Pin #Pin NameSignal DescriptionDirectionPin Type
70DSI_D0_NDSI Data 0–OutputMIPI D-PHY
72DSI_D0_PDSI Data 0+OutputMIPI D-PHY
82DSI_D1_NDSI Data 1–OutputMIPI D-PHY
84DSI_D1_PDSI Data 1+OutputMIPI D-PHY

Table 4: DP/eDP/HDMI Pin Descriptions

Pin #Pin NameSignal DescriptionDirectionPin Type
39DP0_TXD0_NDisplay Port 0 Lane 0-OutputDP/eDP
41DP0_TXD0_PDisplay Port 0 Lane 0+OutputDP/eDP
45DP0_TXD1_NDisplay Port 0 Lane 1–OutputDP/eDP
47DP0_TXD1_PDisplay Port 0 Lane 1+OutputDP/eDP
51DP0_TXD2_NDisplay Port 0 Lane 2–OutputDP/eDP
53DP0_TXD2_PDisplay Port 0 Lane 2+OutputDP/eDP
57DP0_TXD3_NDisplay Port 0 Lane 3–OutputDP/eDP
59DP0_TXD3_PDisplay Port 0 Lane 3+OutputDP/eDP
90DP0_AUX_NDisplay Port 0 Aux–BidirDP/eDP
92DP0_AUX_PDisplay Port 0 Aux+BidirDP/eDP
88DP0_HPDDisplay Port 0 Hot Plug DetectInputOpen Drain – 1.8V
63DP1_TXD0_NHDMI Lane 2–OutputHDMI
65DP1_TXD0_PHDMI Lane 2+OutputHDMI
69DP1_TXD1_NHDMI Lane 1–OutputHDMI
71DP1_TXD1_PHDMI Lane 1+OutputHDMI
75DP1_TXD2_NHDMI Lane 0–OutputHDMI
77DP1_TXD2_PHDMI Lane 0+OutputHDMI
81DP1_TXD3_NHDMI Clk Lane–OutputHDMI
83DP1_TXD3_PHDMI Clk Lane+OutputHDMI
98DP1_AUX_NHDMI DDC SDABidirOpen-Drain, 3.3V
100DP1_AUX_PHDMI DDC SCLOutputOpen-Drain, 3.3V
96DP1_HPDHDMI Hot Plug DetectInputOpen Drain – 1.8V
94HDMI_ CECHDMI CECBidirOpen Drain – 3.3V

Video Output Processor

  • Video ports
    • Video Port0, max output resolution: 7680 x 4320@60 Hz
    • Video Port1, max output resolution: 4096 x 2304@60 Hz
    • Video Port2, max output resolution: 4096 x 2304@60 Hz
    • Video Port3, max output resolution: 1920 x 1080@60 Hz
  • Cluster 0/1/2/3
    • Max input and output resolution 4096 x 2304
    • Support AFBCD
    • Support RGB/YUV/YUYV format
    • Support scale up/down ratio 4~1/4
    • Support rotation
  • ESMART 0/1/2/3
    • Max input and output resolution 4096 x 2304
    • Support RGB/YUV/YUYV format
    • Support scale up/down ratio 8~1/8
    • Support 4 regions
    • Overlay
      • Support up to 8 layers overlay: 4 cluster/4 esmart
      • Support RGB/YUV domain overlay
  • Post process
    • HDR
      • HDR10/HDR HLG
  • Write back
    • Format: ARGB8888/RGB888/RGB565/YUV420
    • Max resolution: 1920 x 1080

Audio Interface

  • I2S0/I2S1 with 8 channels
    • Up to 8 channels TX and 8 channels RX path
    • Audio resolution from 16 bits to 32 bits
    • Sample rate up to 192 KHz
    • Provides master and slave work mode, software configurable
    • Support 3 I2S formats (normal, left-justified, right-justified)
    • Support 4 PCM formats (early, late1, late2, late3)
    • Support TDM normal, 1/2 cycle left shift, 1 cycle left shift, 2 cycle left shift, right shift mode serial audio data transfer
    • I2S, PCM and TDM mode cannot be used at the same time
  • I2S2/I2S3 with 2 channels
    • Up to 2 channels for TX and 2 channels for RX path
    • Audio resolution from 16 bits to 32 bits
    • Sample rate up to 192 KHz
    • Provides master and slave work mode, software configurable
    • Support 3 I2S formats (normal, left-justified, right-justified)
    • Support 4 PCM formats (early, late1, late2, late3)
    • I2S and PCM cannot be used at the same time
    • Support two 16-bit audio data store together in one 32-bit wide location
    • Support bi-phase format stereo audio data output
    • Support 16- to 31-bit audio data left or right justified in 32-bit wide sample data buffer
    • Support 16-, 20-, 24-bit audio data transfer in linear PCM mode
    • Support non-linear PCM transfer
  • PDM0/PDM1
    • Up to 8 channels
    • Audio resolution from 16 bits to 24 bits
    • Sample rate up to 192 KHz
    • Support PDM master receive mode
  • Digital Audio Codec
    • Support 2 channels digital DAC
    • Support I2S/PCM interface, master and slave mode
    • Support 16-bit sample resolution
    • Support three modes of mixing for every digital DAC channel
    • Support volume control
  • VAD (Voice Activity Detection)
    • Support read voice data from I2S/PDM
    • Support voice amplitude detection
    • Support Multi-Mic array data storing
    • Support a level combined interrupt

Table 5: I2S Audio Pin Descriptions

Pin #Pin NameSignal DescriptionDirectionPin Type
199I2S0_SCLKI2S Audio Port 0 ClockBidirCMOS – 1.8V
197I2S0_FSI2S Audio Port 0 Left/Right ClockBidirCMOS – 1.8V
193I2S0_DOUTI2S Audio Port 0 Data OutOutputCMOS – 1.8V
195I2S0_DINI2S Audio Port 0 Data InInputCMOS – 1.8V
226I2S1_SCLKI2S Audio Port 1 ClockBidirCMOS – 1.8V
224I2S1_FSI2S Audio Port 1 Left/Right ClockBidirCMOS – 1.8V
220I2S1_DOUTI2S Audio Port 1 Data OutOutputCMOS – 1.8V
222I2S1_DINI2S Audio Port 1 Data InInputCMOS – 1.8V
124I2S2_DOUTI2S Audio Port 2 Data OutBidirCMOS – 1.8V
126I2S2_DINI2S Audio Port 2 Data InBidirCMOS – 1.8V
127I2S2_FSI2S Audio Port 2 Left/Right ClockInputCMOS – 1.8V
128I2S2_SCLKI2S Audio Port 2 ClockBidirCMOS – 1.8V
112I2S3_DINI2S Audio Port 3 Data InBidirCMOS – 1.8V
218I2S3_DOUTI2S Audio Port 3 Data OutBidirCMOS – 1.8V
130I2S3_FSI2S Audio Port 3 Left/Right ClockBidirCMOS – 1.8V
212I2S3_SCLKI2S Audio Port 3 ClockBidirCMOS – 1.8V


  • SDIO interface
    • Compatible with SDIO3.0 protocol
    • 4-bit data bus width

Table 6: SDIO Pin Descriptions

Pin #Pin NameSignal DescriptionDirectionPin Type
229SDMMC_CLKSD Card or SDIO ClockOutputCMOS – 1.8V/3.3V
227SDMMC_CMDSD Card or SDIO CommandBidirCMOS – 1.8V/3.3V
219SDMMC_DAT0SD Card or SDIO Data 0BidirCMOS – 1.8V/3.3V
221SDMMC_DAT1SD Card or SDIO Data 1BidirCMOS – 1.8V/3.3V
223SDMMC_DAT2SD Card or SDIO Data 2BidirCMOS – 1.8V/3.3V
225SDMMC_DAT3SD Card or SDIO Data 3BidirCMOS – 1.8V/3.3V
  • GMAC 10/100/1000M Ethernet controller
    • Support two Ethernet controllers
    • Support 10/100/1000-Mbps data transfer rates with the RGMII interfaces
    • Support 10/100-Mbps data transfer rates with the RMII interfaces
    • Support both full-duplex and half-duplex operation

Table 7: Gigabit Ethernet Pin Descriptions

Pin #Pin NameSignal DescriptionDirectionPin Type
184GBE_MDI0_NGbE Transformer Data 0–BidirMDI
186GBE_MDI0_PGbE Transformer Data 0+BidirMDI
190GBE_MDI1_NGbE Transformer Data 1–BidirMDI
192GBE_MDI1_PGbE Transformer Data 1+BidirMDI
196GBE_MDI2_NGbE Transformer Data 2–BidirMDI
198GBE_MDI2_PGbE Transformer Data 2+BidirMDI
202GBE_MDI3_NGbE Transformer Data 3–BidirMDI
204GBE_MDI3_PGbE Transformer Data 3+BidirMDI
188GBE_LED_LINKEthernet Link LED (Green)Output
194GBE_LED_ACTEthernet Activity LED (Yellow)Output
  • USB 3.0
    • Embedded two USB 3.0 OTG interfaces which combo with DP TX (USB3OTG_0 and USB3OTG_1)
    • Embedded one USB 3.0 Host interface which combos with Combo PIPE PHY2 (USB3OTG_2)
    • Compatible Specification
      • Universal Serial Bus 3.0 Specification, Revision 1.0
      • Universal Serial Bus Specification, Revision 2.0 (exclude USB3OTG_2)
      • eXtensible Host Controller Interface for Universal Serial Bus (xHCI), Revision 1.1
    • Support Control/Bulk (including stream)/Interrupt/Isochronous Transfer
    • Simultaneous IN and OUT transfer for USB3.0, up to 8 Gbps bandwidth
    • Descriptor caching and data pre-fetching used to improve system performance in high-latency systems
    • LPM protocol in USB 2.0 (exclude USB3OTG_2) and U0, U1, U2, and U3 states for USB 3.0
    • USB3.0 Device Features
      • Up to 10 IN endpoints, including control endpoint 0
      • Up to 6 OUT endpoints, including control endpoint 0
      • Up to 16 endpoint transfer resources, each one for each endpoint
      • Flexible endpoint configuration for multiple applications/USB set-configuration modes
      • Hardware handles ERDY and burst
      • Stream-based bulk endpoints with controller automatically initiating data movement
      • Isochronous endpoints with isochronous data in data buffers
      • Flexible Descriptor with rich set of features to support buffer interrupt moderation, multiple transfers, isochronous, control, and scattered buffering support
    • USB 3.0 xHCI Host Features
      • Support up to 64 devices
      • Support one interrupter
      • Support one USB2.0 port (exclude USB3OTG_2) and one Super-Speed port
      • Support standard or open-source xHCI and class driver
    • USB 3.0 Dual-Role Device (DRD) Features
      • Static Device Operation
      • Static Host Operation
      • USB3.0/USB2.0 OTG A device and B device basing on ID, USB3OTG_2 only support USB3.0
      • Not Support USB3.0/USB2.0 OTG session request protocol (SRP), host negotiation protocol (HNP) and Role Swap Protocol (RSP)
    • Miscellaneous Features
      • USB2.0 PHY support Battery Charge detection
      • USB3OTG_0 and USB3OTG_1 support USB Type-C and DP Alt Mode
      • USB3OTG_2 PHY combos with PCIE and SATA

Table 8: USB3.0 GEN1 Pin Descriptions

Pin #Pin NameSignal DescriptionDirectionPin Type
161USBSS_RX_NUSB SS Receive– (USB 3.0 Ctrl #0)InputUSB SS PHY
163USBSS_RX_PUSB SS Receive+ (USB 3.0 Ctrl #0)InputUSB SS PHY
166USBSS_TX_NUSB SS Transmit– (USB 3.0 Ctrl #0)OutputUSB SS PHY
168USBSS_TX_PUSB SS Transmit+ (USB 3.0 Ctrl #0)OutputUSB SS PHY
  • USB 2.0 Host
    • Compatible with USB 2.0 specification
    • Support two USB 2.0 Hosts
    • Supports high-speed (480 Mbps), full-speed (12 Mbps) and low-speed (1.5 Mbps) mode
    • Support Enhanced Host Controller Interface Specification (EHCI), Revision 1.0
    • Support Open Host Controller Interface Specification (OHCI), Revision 1.0a

Table 9: USB2.0 Pin Descriptions

Pin #Pin NameSignal DescriptionDirectionPin Type
109USB0_D_NUSB2.0 Port 0 Data–BidirUSB PHY
111USB0_D_PUSB2.0 Port 0 Data+BidirUSB PHY
115USB1_D_NUSB 2.0 Port 1 Data–BidirUSB PHY
117USB1_D_PUSB 2.0 Port 1 Data+BidirUSB PHY
121USB2_D_NUSB 2.0 Port 2 Data–BidirUSB PHY
123USB2_D_PUSB 2.0 Port 2 Data+BidirUSB PHY
  • Combo PIPE PHY Interface
    • Support three Combo PIPE PHYs with PCIe2.1/SATA3.0/USB3.0 controller
  • Combo PIPE PHY0 supports one of the following interfaces:
    • SATA
    • PCIe2.1
  • Combo PIPE PHY1 supports one of the following interfaces:
    • SATA
    • PCIe2.1
  • Combo PIPE PHY2 supports one of the following interfaces:
    • SATA
    • PCIe2.1
    • USB3.0
  • PCIe2.1 Interface
    • Compatible with PCI Express Base Specification Revision 2.1
    • Support one lane for each PCIe2.1 interface
    • Support Root Complex (RC) only
    • Support 5 Gbps data rate

Table 10: PCIE2.1 Pin Descriptions

Pin #Pin NameSignal DescriptionDirectionPin Type
167PCIE1_RX0_NPCIe #1 Receive 0– (PCIe Ctrl #2 Lane 0)InputPCIe PHY.
169PCIE1_RX0_PPCIe #1 Receive 0+ (PCIe Ctrl #2 Lane 0)InputPCIe PHY
172PCIE1_TX0_NPCIe #1 Transmit 0– (PCIe Ctrl #2 Lane 0)OutputPCIe PHY
174PCIE1_TX0_PPCIe #1 Transmit 0+ (PCIe Ctrl #2 Lane 0)OutputPCIe PHY
183PCIE1_RST*PCIe #1 Reset (PCIe Ctrl #2). 4.7kΩ pull-up to 3.3V on the module.OutputOpen Drain – 3.3V
182PCIE1_CLKREQ*PCIe #1 Clock Request (PCIe Ctrl #2). 47kΩ pull-up to 3.3V on the module.BidirOpen Drain – 3.3V
173PCIE1_CLK_NPCIe #1 Reference Clock– (PCIe Ctrl #2)OutputPCIe PHY
175PCIE1_CLK_PPCIe #1 Reference Clock+ (PCIe Ctrl #2)OutputPCIe PHY
179PCIE_WAKE*PCIe Wake. 47kΩ pull-up to 3.3V on the module.InputOpen Drain – 3.3V
  • SATA interface
    • Compatible with Serial ATA 3.1 and AHCI revision 1.3.1
    • Support eSATA
    • Support one port for each SATA interface
    • Support 6 Gbps data rate
  • PCIe3.0 interface
    • Compatible with PCI Express Base Specification Revision 3.0
    • Support dual operation modes: Root Complex (RC) and End Point (EP)
    • Support data rates: 2.5 Gbps (PCIe1.1), 5 Gbps (PCIe2.1), 8 Gbps (PCIe3.0)
    • Support aggregation and bifurcation with 1x 4 lanes, 2x 2 lanes, 4x 1 lanes and 1x 2 lanes + 2x 1 lanes

Table 11: PCIE3.0 Pin Descriptions

Pin #Pin NameSignal DescriptionDirectionPin Type
131PCIE0_RX0_NPCIe #0 Receive 0– (PCIe Ctrl #0 Lane 0)InputPCIe PHY
133PCIE0_RX0_PPCIe #0 Receive 0+ (PCIe Ctrl #0 Lane 0)InputPCIe PHY
137PCIE0_RX1_NPCIe #0 Receive 1– (PCIe Ctrl #0 Lane 1)InputPCIe PHY
139PCIE0_RX1_PPCIe #0 Receive 1+ (PCIe Ctrl #0 Lane 1)InputPCIe PHY
134PCIE0_TX0_NPCIe #0 Transmit 0– (PCIe Ctrl #0 Lane 0)OutputPCIe PHY
136PCIE0_TX0_PPCIe #0 Transmit 0+ (PCIe Ctrl #0 Lane 0)OutputPCIe PHY
140PCIE0_TX1_NPCIe #0 Transmit 1– PCIe Ctrl #0 Lane 1)OutputPCIe PHY
142PCIE0_TX1_PPCIe #0 Transmit 1+ (PCIe Ctrl #0 Lane 1)OutputPCIe PHY
181PCIE0_RST*PCIe #0 Reset (PCIe Ctrl #0). 4.7kΩ pull-up to 3.3V on the module.BidirOpen Drain – 3.3V
180PCIE0_CLKREQ*PCIe #0 Clock Request (PCIe Ctrl #0). 47kΩ pull-up to 3.3V on the module.BidirOpen Drain – 3.3V
179PCIE_WAKE*PCIe Wake. 47kΩ pull-up to 3.3V on the module.InputOpen Drain – 3.3V
160PCIE0_CLK_NPCIe #0 Reference Clock–OutputPCIe PHY
162PCIE0_CLK_PPCIe #0 Reference Clock+OutputPCIe PHY
  • SPI interface
    • Support 5 SPI Controllers (SPI0-SPI4)
    • Support two chip-select output
    • Support serial-master and serial-slave mode, software-configurable

Table 12: SPI Pin Descriptions

Pin #Pin NameSignal DescriptionDirectionPin Type
91SPI0_SCKSPI 0 ClockBidirCMOS – 1.8V
89SPI0_MOSISPI 0 Master Out / Slave InBidirCMOS – 1.8V
93SPI0_MISOSPI 0 Master In / Slave OutBidirCMOS – 1.8V
95SPI0_CS0*SPI 0 Chip Select 0BidirCMOS – 1.8V
97SPI0_CS1*SPI 0 Chip Select 1BidirCMOS – 1.8V
106SPI1_SCKSPI 1 ClockBidirCMOS – 1.8V
104SPI1_MOSISPI 1 Master Out / Slave InBidirCMOS – 1.8V
108SPI1_MISOSPI 1 Master In / Slave OutBidirCMOS – 1.8V
110SPI1_CS0*SPI 1 Chip Select 0BidirCMOS – 1.8V
  • I2C Master controller
    • Support 9 I2C Master (I2C0-I2C8)
    • Support 7-bit and 10-bit address mode
    • Software programmable clock frequency
    • Data on the I2C-bus can be transferred at rates of up to 100 Kbps in the Standard-mode, up to 400 Kbps in the Fast-mode

Table 13: I2C Pin Descriptions

Pin #Pin NameSignal DescriptionDirectionPin Type
185I2C0_SCLGeneral I2C 0 Clock. 2.2kΩ pull-up to 3.3V on module.BidirOpen Drain – 3.3V
187I2C0_SDAGeneral I2C 0 Data. 2.2kΩ pull-up to 3.3V on the module.BidirOpen Drain – 3.3V
189I2C1_SCLGeneral I2C 1 Clock. 2.2kΩ pull-up to 3.3V on the module.BidirOpen Drain – 3.3V
191I2C1_SDAGeneral I2C 1 Data. 2.2kΩ pull-up to 3.3V on the module.BidirOpen Drain – 3.3V
232I2C2_SCLGeneral I2C 2 Clock. 2.2kΩ pull-up to 1.8V on the module.BidirOpen Drain – 1.8V
234I2C2_SDAGeneral I2C 2 Data. 2.2kΩ pull-up to 1.8V on the module.BidirOpen Drain – 1.8V
213CAM_I2C_SCLCamera I2C Clock. 2.2kΩ pull-up to 3.3V on the module.BidirOpen Drain – 3.3V
215CAM_I2C_SDACamera I2C Data. 2.2kΩ pull-up to 3.3V on the module.BidirOpen Drain – 3.3V
  • UART interface
    • Support 10 UART interfaces (UART0-UART9)
    • Embedded two 64-byte FIFO for TX and RX operation respectively
    • Support transmitting or receiving 5-bit, 6-bit, 7-bit, and 8-bit serial data
    • Standard asynchronous communication bits such as start, stop and parity
    • Support different input clocks for UART operation to get up to 4 Mbps baud rate
    • Support auto flow control mode for all UART interfaces

Table 14: UART Pin Descriptions

Pin #Pin NameSignal DescriptionDirectionPin Type
99UART0_TXDUART #0 TransmitOutputCMOS – 1.8V
101UART0_RXDUART #0 ReceiveInputCMOS – 1.8V
103UART0_RTS*UART #0 Request to SendOutputCMOS – 1.8V
105UART0_CTS*UART #0 Clear to SendInputCMOS – 1.8V
203UART1_TXDUART #1 TransmitOutputCMOS – 1.8V
205UART1_RXDUART #1 ReceiveInputCMOS – 1.8V
207UART1_RTS*UART #1 Request to SendOutputCMOS – 1.8V
209UART1_CTS*UART #1 Clear to SendInputCMOS – 1.8V
236UART2_TXDUART #2 TransmitOutputCMOS – 1.8V
238UART2_RXDUART #2 ReceiveInputCMOS – 1.8V
  • CAN Bus
    • Support 3 CAN buses
    • Support CAN 2.0B protocol
    • Support transmitting or receiving CAN standard frame
    • Support transmitting or receiving CAN extended frame
    • Support transmitting or receiving data frame, remote frame, overload frame, error frame, and frame interval

Table 15: CAN Pin Descriptions

Pin #Pin NameSignal DescriptionDirectionPin Type


  • Multiple groups of GPIOs
    • All GPIOs can be used to generate interrupt
    • Support level trigger and edge trigger interrupt
    • Support configurable polarity of level trigger interrupt
    • Support configurable rising edge, falling edge and both edge trigger interrupt
    • Support configurable pull direction (a weak pull-up and a weak pull-down)
    • Support configurable drive strength

Table 16: GPIO Pin Descriptions

Pin #Pin NameSignal DescriptionDirectionPin Type
87GPIO00GPIO #0 or USB 0 VBUS Enable #0BidirCMOS – 1.8V
118GPIO01GPIO #1 or Generic ClocksBidirCMOS – 1.8V
124GPIO02GPIO #2BidirCMOS – 1.8V
126GPIO03GPIO #3BidirCMOS – 1.8V
127GPIO04GPIO #4BidirCMOS – 1.8V
128GPIO05GPIO #5BidirCMOS – 1.8V
130GPIO06GPIO #6BidirCMOS – 1.8V
206GPIO07GPIO #7 or Pulse Width ModulatorBidirCMOS – 1.8V
208GPIO08GPIO #8 or Fan TachBidirCMOS – 1.8V
211GPIO09GPIO #9 or Audio Codec Master ClockBidirCMOS – 1.8V
212GPIO10GPIO #10BidirCMOS – 1.8V
216GPIO11GPIO #11 or Generic ClocksBidirCMOS – 1.8V
218GPIO12GPIO #12 or Pulse Width ModulatorBidirCMOS – 1.8V
228GPIO13GPIO #13 or Pulse Width ModulatorBidirCMOS – 1.8V
230GPIO14GPIO #14 or Pulse Width ModulatorBidirCMOS – 1.8V
  • Temperature Sensor (TS-ADC)
    • Support User-Defined Mode and Automatic Mode
    • In User-Defined Mode, start_of_conversion can be controlled completely by software, and also can be generated by hardware
    • In Automatic Mode, the temperature of alarm (high/low temperature) interrupt can be configurable
    • In Automatic Mode, the temperature of system reset can be configurable
    • Support up to 7 channels TS-ADC, the temperature criteria of each channel can be configurable
    • -40~125°C temperature range and 1°C temperature resolution
  • Successive approximation register ADC (SAR ADC)
    • 12-bit resolution
    • Up to 1 MS/s sampling rate
    • Eight single-ended input channels
  • OTP
    • Support 32 Kbit address space and the higher 4 Kbit address space is non-secure part
    • Support read and program word mask in secure model
    • Support maximum 32-bit OTP program operation
    • Support maximum 16-word OTP read operation
    • Program and Read state can be read
    • Program fail address record
  • Package Type
    • FCBGA1088L (body: 23 mm x 23 mm; ball size: 0.36 mm; ball pitch: 0.65 mm)

Power and System Management

Power and System Management

VIN must be supplied by the carrier board that the module is designed to connect to. All interfaces are referenced to on- module voltage rails, additional I/O voltage is not required to be supplied to the module.
Table 17: Power and System Control Pin Descriptions

Pin #Pin NameSignal DescriptionDirectionPin Type
VDD_INMain power – Supplies PMIC and other registersInput5.0V
235PMIC_BBATPMIC Battery Back-up. Optionally used to provide back-up power for the Real-Time Clock (RTC). Connects to Lithium Cell or super capacitor on Carrier Board. PMIC is supply when charging cap or coin cell. Super cap or coin cell is source when system is disconnected from power.Bidir1.65V-5.5V
233SHUTDOWN_REQ*Used by the module to request a shutdown from the carrier board. Pull up to VDD_IN_5V with 4.7 kΩ on the module.OutputAnalog – 5.0V
237POWER_ENSignal for module on/off: high level on, low level off. Connects to module PMIC EN0 through converter logic.
POWER_EN is routed to a Schmitt trigger buffer on the module. A 45 kΩ pullup is in the PMIC.
InputCMOS – 5.0V
239SYS_RESET*Module Reset. Reset to the module when driven low by the carrier board. Used as carrier board supply enable when driven high by the module when module power sequence is complete. Used to ensure proper power on/off sequencing between module and carrier board supplies. Pull up to 1.8 V with 10 kΩ resistor on the module.BidirOpen Drain
– 1.8V
178MOD_SLEEP*Module Sleep. When active (low), indicates module has gone to Sleep (SC7) mode.OutputCMOS – 3.3V
210CLK_32K_OUTSleep/Suspend clockOutputCMOS – 1.8V
214FORCE_RECOVERY*Force Recovery strap pinInputCMOS – 1.8V
240SLEEP/WAKE*Configured as GPIO for optional use to indicate the system should enter or exit sleep mode.InputCMOS – 5.0V

Power Management Controller (PMC)

The PMC power management features enable both high speed operation and very low-power standby states. The PMC primarily controls voltage transitions for the SoC as it transitions to/from different low power modes; it also acts as a slave receiving dedicated power/clock request signals as well as wake events from various sources (e.g., SPI, I2C, RTC, USB) which can wake the system from deep sleep state. The PMC enables aggressive power-gating capabilities on idle modules and integrates specific logic to maintain defined states and control power domains during sleep and deep sleep modes.


If you assert reset, the Mixtile Core 3588E and onboard storage will be reset. This signal is also used for baseboard power sequencing.


An optional backup battery can be attached to the VCC_RTC module input to maintain the module RTC when VIN is not present. This pin is connected directly to the onboard PMIC. Details of the types of backup cells that optionally can be connected are found in the PMIC manufacturer’s data sheet. When a backup cell is connected to the PMIC, the RTC retains its contents and can be configured to charge the backup cell as well. RTC accuracy is 2 seconds/day in typical room temperature only.
The following backup cells may be attached to this pin:

  • Super capacitor (gold cap, double layer electrolytic)
  • Standard capacitors (tantalum)
  • Rechargeable Lithium Manganese cells

The backup cells must provide a voltage in the range 2.5 V to 3.5 V.

Power Sequencing

Mixtile Core 3588E is required to be powered on and off in a known sequence. Sequencing is determined through a set of control signals; the SYS_RESET* signal (when deasserted) is used to indicate when the carrier board can power on. The following sections provide an overview of the power sequencing steps between the carrier board and Mixtile Core 3588E. The Mixtile Core 3588E and the product carrier board must be power sequenced properly to avoid potential damage to components on either the module or the carrier board system.

Power Up

During power-up, the carrier board must wait until the signal SYS_RESET* is deasserted from the Mixtile Core 3588E before enabling its power; the Mixtile Core 3588E deasserts the SYS_RESET* signal to enable the complete system to boot.

Power Down

Shutdown events can be triggered by either the module or the baseboard, but the shutdown event is always serviced by the baseboard. To do so, the baseboard deasserts POWER_EN, which begins the shutdown power sequence on the module. If the module needs to request a shutdown event in the case of thermal, software, or under-voltage events, it asserts SHUTDOWN_REQ*. When the baseboard sees low SHUTDOWN_REQ*, it should deassert POWER_EN as soon as possible.
Once POWER_EN is deasserted, the module asserts SYS_RESET*, and the baseboard may shut down. SoC 3.3 V I/O must reach 0.5 V or lower at most 1.5 ms after SYS_RESET* is asserted. SoC 1.8 V I/O must reach 0.5 V or lower at most 4 ms after SYS_RESET* is asserted.

Block Diagram

Pin Definition

The following table lists the pin definition of Core 3588E. For pin comparisons with Jetson TX2 NX and Jetson Orin Nano, see this file CORE3588E_Pin_Function Comparison with Jetson TX2 NX and Jetson Orin Nano.

Core 3588E FunctionPin NumberPin NumberCore 3588E Function

Technical Support

MIXTILE technical support team assists you with the questions you may have. Contact us with the following methods below.

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