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Mixtile Blade 3 is a low-cost, low-power single-board computer (SBC) based on the next-generation, 8 nm Rockchip RK3588 CPU. It is ideal for quick development, AI-application prototyping, and edge computing, and it allows you to extend your deployment by clustering several Mixtile Blade 3 SBCs. It also features a 4-lane PCIe Gen3 port for communicating with other processing nodes, allowing for high-performance computing with minimal carbon footprint.

Main Features

  • CPU: Rockchip Octa-core Cortex-A76/A55 SoC processor RK3588
  • NPU: Up to 6 TOPS
  • Memory: Up to 32 GB LPDDR4/LPDDR5 memory, up to 256 GB eMMC storage
  • HDMI interface: HDMI 2.1 output (8K @ 60 FPS or 4K @ 120 FPS), HDMI 2.0 input (4K @ 60 FPS)
  • Video encoder: H.264/H.265 video encoder up to 8K @ 30 FPS
  • Video decoder: H.265/H.264/VP9 video decoder up to 8K @ 60 FPS
  • Camera Input: 4-lane MIPI-CSI
  • PCIe expansion: Mini-PCIe socket with PCIe Gen 2.1, USB 2.0 support
  • Storage expansion: 4-lane PCIe Gen 3 in U.2 port, SATA 3.0 in U.2 port, Micro-SD 3.0 flash socket
  • Ethernet expansion: Dual 2.5 gigabit Ethernet ports
  • USB: Dual USB 3.2 Gen 1 Type-C ports, DisplayPort 1.4 A
  • GPIOs: 30-pin GPIO socket (Digital I/O, I²C, USB 2.0, TTL UART, SPI, I²S)
  • Software support: Preloaded customized Debian 11, Support other Linux distributions and Android 12 (**will release in future**)
  • Power: USB1/PD Type-C Port support USB PD 2.0 protocol (Optional: 12 V DC standard SATA power via U.2 port)
  • Dimensions: 2.5-inch Pico-ITX form factor, 100 mm x 72 mm

Connectors and Pinouts

Block Diagram

The block diagram of the Blade 3 SBC is shown below, along with descriptions of each connector and pinout.

Specs Layout

The specification layout is depicted in the picture below, along with the ports accessible on Blade 3 for application-based development.


Connectors & Pinouts Description

This section lists the interfaces connector pin assignments and pin types with signal descriptions.

Table 1. 30-PIN Header

1VCC_5V0PowerOutputPower supply  for USB, 5 V output MAX 500 mA
2GNDPowerNAPower and signal reference ground
4I2S2_SDI_M1signalInputI2S2 data input
6I2S2_SDO_M1signalOutputI2S2 data output
7GNDPowerNAPower and signal reference ground
8I2S2_MCLK_M1signalOutputI2S2 Master clock
9I2C5_SDA_M3signalBII2C5 Bus Date
10I2S2_SCLK_M1signalBII2S2 serial clock or BCLK
11I2C5_SCL_M3signalOutputI2C5 Bus clock
12I2S2_LRCK_M1signalBII2S2 Left/Right channel clock
13GNDPowerNAPower and signal reference ground
14GNDPowerNAPower and signal reference ground
15SPI4_MISO_M2signalInputSPI4 Master input, Slave output
16CAN2_RXsignalInputCAN2 receive data
17SPI4_MOSI_M2signalOutputSPI4 Master output, Slave input
18CAN2_TXsignalOutputCAN2 transmit data
19SPI4_CLK_M2signalOutputSPI4 clock
20GNDPowerNAPower and signal reference ground
21SPI4_CS0_M2signalOutputSPI4 Chip Select 0
22GPIO0_B0signalBIGPIO bank 0 port B0
23GPIO1_A4signalBIGPIO bank 1 port A4
24SARADC_VIN7AnalogInputSAR ADC Channel 7 input
25GNDPowerNAPower and signal reference ground
26SARADC_VIN6AnalogInputSAR ADC Channel 6 input
27PWM14signalBIPulse Width Modulation 14 input or output
28GNDPowerNAPower and signal reference ground
29PWM15signalBIPulse Width Modulation 15 input or output
30VCC_3V3_S0PowerOutputPower supply for peripheral, 3.3 V output MAX 500 mA

Table. 2PIN FAN

1VCC5V_FANPowerOutputPower supply  for FAN, 5 V output MAX 400 mA. Controlled by GPIO3_C0
2GNDPowerNAPower reference ground

Table 3. mini-PCIe

1MINIPCIE20_WAKEN_3V3_LsignalInputWake up signal from mini-PCIe device
2VCC3V3_MINIPCIEPowerOutputPower supply  for mini-PCIe device, 3.3 V output MAX 3A in all pins
3NCfloatNANot connected to this pin
4GNDPowerNAPower and signal reference ground
5NCfloatNANot connected to this pin
6NCfloatNANot connected to this pin
7MINIPCIE20_CLKREQN_3V3_LsignalInputPCIe2.0 Channel Reference clock request
8NCfloatNANot connected to this pin
9GNDPowerNAPower and signal reference ground
10NCfloatNANot connected to this pin
11PCIE20_2_REFCLKNLVDSOutputPCIe20 Port2 differential clock Negative
12NCfloatNANot connected to this pin
13PCIE20_2_REFCLKPLVDSOutputPCIe20 Port2 differential clock Positive
14NCfloatNANot connected to this pin
15GNDPowerNAPower and signal reference ground
16NCfloatNANot connected to this pin
17NCfloatNANot connected to this pin
18GNDPowerNAPower and signal reference ground
19NCfloatNANot connected to this pin
20W_DISABLENsignalOutputPCIE device wireless disable
21GNDPowerNAPower and signal reference ground
22MINIPCIE20_PERSTNsignalOutputPCIe device reset
23PCIE20_2_RXNLVDSInputPCIe20 receive differential Negative
24VCC3V3_MINIPCIEPowerOutputPower supply  for mini-PCIe device, 3.3 V output MAX 3A in all pins
25PCIE20_2_RXPLVDSInputPCIe20 receive differential Positive
26GNDPowerNAPower and signal reference ground
27GNDPowerNAPower and signal reference ground
28NCfloatNANot connected to this pin
29GNDPowerNAPower and signal reference ground
30NCfloatNANot connected to this pin
31MINIPCIE20_TX_NLVDSOutputPCIe20 transmit differential Negative
32NCfloatNANot connected to this pin
33MINIPCIE20_TX_PLVDSOutputPCIe20 transmit differential Positive
34GNDPowerNAPower and signal reference ground
35GNDPowerNAPower and signal reference ground
37GNDPowerNAPower and signal reference ground
39VCC3V3_MINIPCIEPowerOutputPower supply  for mini-PCIe device, 3.3 V output MAX 3 A in all pins
40GNDPowerNAPower and signal reference ground
41VCC3V3_MINIPCIEPowerOutputPower supply  for mini-PCIe device, 3.3 V output MAX 3 A in all pins
42NCfloatNANot connected to this pin
43GNDPowerNAPower and signal reference ground
44NCfloatNANot connected to this pin
45NCfloatNANot connected to this pin
46NCfloatNANot connected to this pin
47NCfloatNANot connected to this pin
48NCfloatNANot connected to this pin
49NCfloatNANot connected to this pin
50GNDPowerNAPower and signal reference ground
51NCfloatNANot connected to this pin
52VCC3V3_MINIPCIEPowerOutputPower supply  for mini-PCIe device, 3.3 V output MAX 3 A in all pins

Table 4. 30-PIN MIPI-CSI

1GNDPowerNAPower and signal reference ground
2MIPI_CSI0_RX_D0NLVDSInputMIPI CSI0 receive  differential data lane 0 Negative
3MIPI_CSI0_RX_D0PLVDSInputMIPI CSI0 receive  differential data lane 0 Positive
4GNDPowerNAPower and signal reference ground
5MIPI_CSI0_RX_D1NLVDSInputMIPI CSI0 receive  differential data lane 1 Negative
6MIPI_CSI0_RX_D1PLVDSInputMIPI CSI0 receive  differential data lane 1 Positive
7GNDPowerNAPower and signal reference ground
8MIPI_CSI0_RX_CLK0NLVDSInputMIPI CSI0 receive  differential Clock 0 Negative
9MIPI_CSI0_RX_CLK0PLVDSInputMIPI CSI0 receive  differential Clock 0 Positive
10GNDPowerNAPower and signal reference ground
11MIPI_CSI0_RX_D2NLVDSInputMIPI CSI0 receive  differential data lane 2 Negative
12MIPI_CSI0_RX_D2PLVDSInputMIPI CSI0 receive  differential data lane 2 Positive
13GNDPowerNAPower and signal reference ground
14MIPI_CSI0_RX_D3NLVDSInputMIPI CSI0 receive  differential data lane 3 Negative
15MIPI_CSI0_RX_D3PLVDSInputMIPI CSI0 receive  differential data lane 3 Positive
16GNDPowerNAPower and signal reference ground
17MIPI_CAM_PWM2signalOutputPWM2 for LENS
18NCfloatNANot connected to this pin
19VCC_3V3_S0PowerOutputPower supply for sensor board, 3.3 V output
20MIPI_CAM_RESETNsignalOutputGPIO out for sensor reset
21NCfloatNANot connected to this pin
22MIPI_CAM_PDNsignalOutputGPIO out for sensor power down
23I2C3_SDA_M3_MIPIsignalBII2C5 Bus data
24I2C3_SCL_M3_MIPIsignalOutputI2C5 Bus clock
25GNDPowerNAPower and signal reference ground
26MIPI_CAM2_CLK_M1_3V3signalOutputCamera Master clock output
27GNDPowerNAPower and signal reference ground
28VCC_5V0PowerOutputPower supply for sensor board, 5 V output
29VCC_5V0PowerOutputPower supply for sensor board, 5 V output
30VCC_5V0PowerOutputPower supply for sensor board, 5 V output

Table 5. U.2 Plug

E1PCIE30_REFCLKP_SLOTLVDSOutputRC PCIe30 differential clock Positive
E2PCIE30_REFCLKN_SLOTLVDSOutputRC PCIe30 differential clock Negative
E3VCC_3V3_S0PowerOutputPower supply for IO
E4PCIE30X4_CLKREQN_M1_LsignalOutputDM PCIe30 Channel Reference clock request
E5PCIE30X4_PERSTN_M1_LsignalInputDM PCIe30 Channel reset
E6PCIE30X4_CLKREQN_M3signalInputRC PCIe30 Channel Reference clock request
E7PCIE30_PORT1_REFCLKPLVDSInputDM PCIe30 differential clock Positive
E8PCIE30_PORT1_REFCLKNLVDSInputDM PCIe30 differential clock Negative
E9GNDPowerNAPower and signal reference ground.
E10PCIE30_PORT1_TX2PLVDSOutputDM PCIe30 transmit differential Positive
E11PCIE30_PORT1_TX2NLVDSOutputDM PCIe30 transmit differential Negative
E12GNDPowerNAPower and signal reference ground
E13PCIE30_PORT1_RX2NLVDSInputDM PCIe30 receive differential Negative
E14PCIE30_PORT1_RX2PLVDSInputDM PCIe30 receive differential Positive
E15GNDPowerNAPower and signal reference ground
E16NCfloatNANot connected to this pin
E17PCIE30_PORT0_RX1PLVDSInputRC PCIe30 receive differential Negative
E18PCIE30_PORT0_RX1NLVDSInputRC PCIe30 receive differential Positive
E19GNDPowerNAPower and signal reference ground
E20PCIE30_PORT0_TX1NLVDSOutputRC PCIe30 transmit differential Positive
E21PCIE30_PORT0_TX1PLVDSOutputRC PCIe30 transmit differential Negative
E22GNDPowerNAPower and signal reference ground
E23I2C4_SCL_M0signalOutputI2C4 Bus clock
E24I2C4_SDA_M0signalBII2C4 Bus data
E25DUALPORT_EN#signalOutputGPIO for Enable dual port, default low
P1PCIE30X4_WAKEN_M1_LsignalOutputDM PCIE30 Wake up signal from RC
P2PCIE30X4_WAKEN_M3signalInputRC PCIE30 Wake up signal from DM
P3PWRDISsignalOutputGPIO for power disable to device
P4IFDETsignalInputGPIO for detect interface of device
P5GNDPowerNAPower and signal reference ground
P6GNDPowerNAPower and signal reference ground
P7NCfloatNANot connected to this pin
P8NCfloatNANot connected to this pin
P9NCfloatNANot connected to this pin
P10PRSNT#signalInputGPIO for detect  device if present
P11ACTIVITY#signalInputGPIO for detect  device if activity
P12GNDPowerNAPower and signal reference ground
P13U2_12VPowerInputPower supply for blade3, input 12 V
P14U2_12VPowerInputPower supply for blade3, input 12 V
P15U2_12VPowerInputPower supply for blade3, input 12 V
S1GNDPowerNAPower and signal reference ground
S2SATA0_TXPLVDSOutputSATA30 Port0 transmit differential Positive
S3SATA0_TXNLVDSOutputSATA30 Port0 transmit differential Negative
S4GNDPowerNAPower and signal reference ground
S5SATA0_RXNLVDSInputSATA30 Port0 receive differential Positive
S6SATA0_RXPLVDSInputSATA30 Port0 receive differential Negative
S7GNDPowerNAPower and signal reference ground
S8GNDPowerNAPower and signal reference ground
S9NCfloatNANot connected to this pin
S10NCfloatNANot connected to this pin
S11GNDPowerNAPower and signal reference ground
S12NCfloatNANot connected to this pin
S13NCfloatNANot connected to this pin
S14GNDPowerNAPower and signal reference ground
S15PCIE30X4_PERSTN_M3signalOutputRC PCIe30 Channel reset
S16GNDPowerNAPower and signal reference ground
S17PCIE30_PORT1_TX3PLVDSOutputDM PCIe30 transmit differential Negative
S18PCIE30_PORT1_TX3NLVDSOutputDM PCIe30 transmit differential Positive
S19GNDPowerNAPower and signal reference ground
S20PCIE30_PORT1_RX3NLVDSInputDM PCIe30 receive differential Negative
S21PCIE30_PORT1_RX3PLVDSInputDM PCIe30 receive differential Positive
S22GNDPowerNAPower and signal reference ground
S23PCIE30_PORT0_RX0PLVDSInputRC PCIe30 receive differential Negative
S24PCIE30_PORT0_RX0NLVDSInputRC PCIe30 receive differential Positive
S25GNDPowerNAPower and signal reference ground
S26PCIE30_PORT0_TX0NLVDSOutputRC PCIe30 transmit differential Negative
S27PCIE30_PORT0_TX0PLVDSOutputRC PCIe30 transmit differential Positive
S28GNDPowerNAPower and signal reference ground

Table 6. 3-PIN DEBUG Header

1UART2_RX_M0_DEBUGsignalIntputUART2 Receive Data for debug
2UART2_TX_M0_DEBUGsignalOutputUART2 Transmit Data for debug
3GNDsignalNAPower and signal reference ground

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