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Data Sheet


Mixtile Cluster Box is a PCIe switcher that can mount up to four Mixtile Blade 3s through PCIe interfaces, which allows for multi-node computation. Comparing with a single Blade 3 board, this powerful and versatile 4-node clustering offers boosted computing performance, faster networking, and expansive storage capacity.

The switcher consists of a backplane and a control board enclosed in a customized chassis with dual cooling fans. Thanks to the ASM2824 PCIe switch chip, the quad-channel PCIe 3.0 backplane enables seamless data transmission between Blade 3 boards for robust, uninterrupted performance.

Main Features

  • Boosted computational performance

A 4-node cluster enhances computational capabilities, which enables you to easily tackle complex tasks, process data-intensive applications, and accelerate your workflows.

  • Seamless connectivity and uninterruptible data transmission

Driven by the ASM2824 PCIe Packet Switch chip, the cutting-edge backplane ensures seamless connectivity among Blade 3s and continuous data transmission.

  • Expanded storage capacity

Four NVMe M.2 slots support PCIe 3.0 x2, which are fully compatible with SSDs. You can scale out storage without compromising on storing critical data or large-scale projects.

  • Compact size with efficient cooling system

A customized small chassis equipped with two internal 60 mm fans ensures that your system runs stably and smoothly in a very small format.

Technical Specifications

SwitchASMedia ASM2824, support four PCIe 3.0 4-lane ports
Storage interfaces4x NVMe M.2 M-Key slot (PCIe 3.0 x2 each slot, connecting to Blade 3)4x SATA 3.0 port (connecting to Blade 3)
Connectivity4x U.2 interfaces (connecting to Blade 3)
Network1x 100/1000 Mbps Ethernet port
PCIe expansion2x SFF-8643 port (support PCIe 3.0 x4 each, upstream)
Fan2x 60 mm fans
Software supportPreloaded customized Linux system and Kubernetes
Power1x DC jack port, 19~19.5 V 4.74 A power inputPower button with a blue LED indicator
MaterialMetal case, SGCC steel
Dimensions213 mm x 190 mm x 129 mm
TemperatureOperating: 0°C to 80°CStorage: -20°C to 85°C
Relative humidityOperating: 10% to 90%Storage: 5% to 95%

Functional Description


MediaTek MT7620A router-on-a-chip

  • Embedded MIPS24KEc (580 MHz) with 64 KB I-Cache and 32 KB D-Cache
  • 256 Mbytes DDR2
  • 16 Mbytes SPI Flash
  • Firmware: OpenWrt System


ASM2824 PCIe Packet switch

  • Upstream PCIe interface
  • 1-, 2-, 4-, or 8-lane PCIe® connecting with root port
  • Automatic detection of lane configuration on boot-up
  • Supporting transfer rate of 2.5 Gb (250 MB/s), 5 Gb (500 MB/s) per lane
  • Downstream PCIe interface
  • 16 lane PCIe® 3.1 interface supporting up to 12 PCIe® ports
  • Support L0s/L1/L23/L3 power saving states
  • Support L1 substate deep power saving mode
  • Support wake up function in S3/S4
  • Support port disable by individual control
  • Support LTR
  • Support AER
  • Support SRIS on both upstream and downstream ports.
  • Max Payload Size = 512 Byte
  • Support hot-plug, surprise remove


U.2 Interface

The U.2 interface employs a 68-pin U.2 connector with a standard SATA signal, a SATA3.0 signal,a PCIe 3.0 X4 signal (four lanes PCIe 3.0), and 12 V or 19 V power output for main board.

Table 1: U.2 Pin Descriptions

Pin #Pin NameSignal DescriptionDirectionPin Type
8PCIE30_PORT1_REFCLKPPCIE3.0 Reference Clock1+InputPCIe PHY
9PCIE30_PORT1_REFCLKNPCIE3.0 Reference Clock1–InputPCIe PHY
11PCIE30X4_CLKREQNPCIE3.0 Clock RequestBidirOpen Drain–3.3V
12PCIE30X4_PERSTNPCIE3.0 ResetBidirOpen Drain–3.3V
14PCIE30X4_WAKENPCIE3.0 WakeInputOpen Drain–3.3V
17M.2_DETM.2 Plug DetectInputOpen Drain–3.3V
22LEDLED PowerInputPower
2619V19V main PowerOutputPower
2719V19V Main PowerOutputPower
2819V19V Main PowerOutputPower
33PCIE30_PORT0_TX3PPCIe3.0 Transmit 3+OutputPCIe PHY
34PCIE30_PORT0_TX3NPCIe3.0 Transmit 3–OutputPCIe PHY
36PCIE30_PORT0_RX3NPCIe3.0 Receive 3–InputPCIe PHY
37PCIE30_PORT0_RX3PPCIe3.0 Receive 3+InputPCIe PHY
39PCIE30_PORT0_TX2PPCIe3.0 Transmit 2+OutputPCIe PHY
40PCIE30_PORT0_TX2NPCIe3.0 Transmit 2–OutputPCIe PHY
42PCIE30_PORT0_RX2NPCIe3.0 Receive 2–InputPCIe PHY
43PCIE30_PORT0_RX2PPCIe3.0 Receive 2+InputPCIe PHY
45PCIE30_PORT0_TX1PPCIe3.0 Transmit 1+OutputPCIe PHY
46PCIE30_PORT0_TX1NPCIe3.0 Transmit 1–OutputPCIe PHY
48PCIE30_PORT0_RX1NPCIe3.0 Receive 1–InputPCIe PHY
49PCIE30_PORT0_RX1PPCIe3.0 Receive 1+InputPCIe PHY
51POWER_ONMB Power on control GPIOBidirOpen Drain–3.3V
56UART_TXDUART TransmitOutputCMOS–3.3V
57UART_RXDUART ReceiveInputCMOS–3.3V
59RESETMB Reset control GPIOBidirOpen Drain–3.3V
61PCIE30_PORT0_TX0PPCIe3.0 Transmit 0+OutputPCIe PHY
62PCIE30_PORT0_TX0NPCIe3.0 Transmit 0–OutputPCIe PHY
64PCIE30_PORT0_RX0NPCIe3.0 Receive 0–InputPCIe PHY
65PCIE30_PORT0_RX0PPCIe3.0 Receive 0+InputPCIe PHY
67DPE_CLKN0PCIE3.0 Reference Clock0+InputPCIe PHY
68DPE_CLKP0PCIE3.0 Reference Clock0–InputPCIe PHY

M.2 Interface

The M.2 interface employs a 77-pin M.2 connector with a standard PCIE3.0 X2 signal, and for PCIE Module 3.3 V power Output. It can be used for external SSD to increase storage capacity.

Table 2: M.2 Pin Descriptions

Pin #Pin NameSignal DescriptionDirectionPin Type
3M.2_DETM.2 Plug DetectInputOpen Drain–3.3V
29M2_PCIE30_PORT0_RX1NPCIe3.0 Receive 1–InputPCIe PHY
31M2_PCIE30_PORT0_RX1PPCIe3.0 Receive 1+InputPCIe PHY
35M2_PCIE30_PORT0_TX1NPCIe3.0 Transmit 1-OutputPCIe PHY
37M2_PCIE30_PORT0_TX1PPCIe3.0 Transmit 1+OutputPCIe PHY
41M2_PCIE30_PORT0_RX0NPCIe3.0 Receive 0–InputPCIe PHY
43M2_PCIE30_PORT0_RX0PPCIe3.0 Receive 0+InputPCIe PHY
47M2_PCIE30_PORT0_TX0NPCIe3.0 Transmit 0-OutputPCIe PHY
49M2_PCIE30_PORT0_TX0PPCIe3.0 Transmit 0+OutputPCIe PHY
53PCIE30_PORT1_REFCLKNPCIE3.0 Reference Clock1+InputPCIe PHY
55PCIE30_PORT1_REFCLKPPCIE3.0 Reference Clock1–InputPCIe PHY
2VCC3V3_PCIE3.3V M.2 Module PowerOutputPower
4VCC3V3_PCIE3.3V M.2 Module PowerOutputPower
12VCC3V3_PCIE3.3V M.2 Module PowerOutputPower
14VCC3V3_PCIE3.3V M.2 Module PowerOutputPower
16VCC3V3_PCIE3.3V M.2 Module PowerOutputPower
18VCC3V3_PCIE3.3V M.2 Module PowerOutputPower
50PCIE30X4_PERSTnPCIE3.0 ResetBidirOpen Drain–3.3V
52PCIE30X4_CLKREQnPCIE3.0 Clock RequestBidirOpen Drain–3.3V
54PCIE30X4_WAKENPCIE3.0 WakeInputOpen Drain–3.3V
70VCC3V3_PCIE3.3V M.2 Module PowerOutputPower
72VCC3V3_PCIE3.3V M.2 Module PowerOutputPower
74VCC3V3_PCIE3.3V M.2 Module PowerOutputPower

100/1000 Mbps Ethernet Controller

  • Support two identical Ethernet controllers
  • Support 10/100 Mbps data transfer rates with the RGMII interfaces
  • Support 10/100 Mbps data transfer rates with the RMII interfaces
  • Support both full-duplex and half-duplex operation
  • Supports IEEE 802.1Q VLAN tag detection for reception frames
  • Support detection of LAN wake-up frames and AMD Magic Packet frames
  • Support checking IPv4 header checksum and TCP, UDP, or ICMP checksum encapsulated in IPv4 or IPv6 datagram
  • Support for TCP Segmentation Offload (TSO) and UDP Fragmentation Offload (UFO)

SATA Interface

  • Compatible with Serial SATA 3.3 and AHCI Revision 1.3.1
  • Support eSATA
  • Support 1.5 Gb/s, 3.0 Gb/s, 6.0 Gb/s
  • Support 3 SATA controller


  • Compliant with the latest SAS 3.0 spec, and supports 12 Gb/s data transfer protocol
  • Support up to 4-ports (4 lanes) of SAS data.

Table 3: SFF-8643 Pin Descriptions

Pin #Pin NameSignal DescriptionDirectionPin Type
A1CLK0P_8643SFF-8643 SAS Reference Clock+OutputPCIe PHY
A2CLK0N_8643SFF-8643 SAS Reference Clock-OutputPCIe PHY
A4UPE_RXP1SFF-8643 SAS Receive 1+InputPCIe PHY
A5UPE_RXN1SFF-8643 SAS Receive 1-InputPCIe PHY
A7UPE_RXP3SFF-8643 SAS Receive 3+InputPCIe PHY
A8UPE_RXN3SFF-8643 SAS Receive 3-InputPCIe PHY
C4UPE_TXP1SFF-8643 SAS Transmit 1+OutputPCIe PHY
C5UPE_TXN1SFF-8643 SAS Transmit 1-OutputPCIe PHY
C7UPE_TXP3SFF-8643 SAS Transmit 3+OutputPCIe PHY
C8UPE_TXN3SFF-8643 SAS Transmit 3-OutputPCIe PHY
B18643_RESETSFF-8643 Reset controlBidirOpen Drain–3.3V
B28643_SELSFF-8643 SEL GPIOBidirCMOS–3.3V
B48643_RXP0SFF-8643 SAS Receive 0+InputPCIe PHY
B58643_RXN0SFF-8643 SAS Receive 0-InputPCIe PHY
B7UPE_RXP2SFF-8643 SAS Receive 2+InputPCIe PHY
B8UPE_RXN2SFF-8643 SAS Receive 2-InputPCIe PHY
D48643_TXP0SFF-8643 SAS Transmit 0+OutputPCIe PHY
D58643_TXN0SFF-8643 SAS Transmit 0-OutputPCIe PHY
D7UPE_TXP2SFF-8643 SAS Transmit 2+OutputPCIe PHY
D8UPE_TXN2SFF-8643 SAS Transmit 2-OutputPCIe PHY


The leading connector for system DEBUG.

Table 4: UART Pin Descriptions

Pin #Pin NameSignal DescriptionDirectionPin Type
1UART_RXUART ReceiveBidirPower
2UART_TXUART TransmitBidirOpen Drain–3.3V

Block Diagram

Technical Support

MIXTILE technical support team assists you with the questions you may have. Contact us with the following methods below.

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